[IAI,LV] Avoid creating interleave-groups for predicated accesse
authorDorit Nuzman <dorit.nuzman@intel.com>
Sun, 7 Oct 2018 06:57:25 +0000 (06:57 +0000)
committerDorit Nuzman <dorit.nuzman@intel.com>
Sun, 7 Oct 2018 06:57:25 +0000 (06:57 +0000)
commit72f6e29980ab32c9519096e9688f2a543a99f639
treec00c1d60a68d7326d1e679b25fdb85bec2ac6fef
parent47afe5e7c058d1f2900e7f1dee4bbe857ca6c249
[IAI,LV] Avoid creating interleave-groups for predicated accesse

This patch fixes PR39099.

When strided loads are predicated, each of them will form an interleaved-group
(with gaps). However, subsequent stages of vectorization (planning and
transformation) assume that if a load is part of an Interleave-Group it is not
predicated, resulting in wrong code - unmasked wide loads are created.

The Interleaving Analysis does take care not to have conditional interleave
groups of size > 1, but until we extend the planning and transformation stages
to support masked-interleave-groups we should also avoid having them for
size == 1.

Reviewers: Ayal, hsaito, dcaballe, fhahn

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D52682

llvm-svn: 343931
llvm/lib/Analysis/VectorUtils.cpp
llvm/test/Transforms/LoopVectorize/X86/x86-pr39099.ll [new file with mode: 0644]
llvm/test/Transforms/LoopVectorize/pr39099.ll [new file with mode: 0644]