[RISCV] Make zve32f imply F and zve64d imply D.
authorCraig Topper <craig.topper@sifive.com>
Sun, 7 May 2023 06:17:16 +0000 (23:17 -0700)
committerCraig Topper <craig.topper@sifive.com>
Sun, 7 May 2023 06:17:16 +0000 (23:17 -0700)
commit728b8a139804db4fd9bce1ac7fa3dcbaf4dc316c
tree668caa02d8aacef8644152d6b5e94230a20aa183
parentdf722b01246de56a1d3c6f5b1e7aaa881c39f642
[RISCV] Make zve32f imply F and zve64d imply D.

The 1.0 vector spec PDF has text that says that Zve32f is compatible
with F or Zfinx and that Zve64d is compatible with D and Zdinx.
The references to *inx were removed from the spec in the github repository in
October 2021. The 1.0 pdf was made in September 2021.

Relevant commit https://github.com/riscv/riscv-v-spec/commit/6fedb869e213da03f36092d661d14911a2f9d2c6

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D150021
clang/test/Driver/riscv-arch.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td