riscv: dts: add initial support for the SiFive FU540-C000 SoC
authorPaul Walmsley <paul.walmsley@sifive.com>
Tue, 28 May 2019 06:34:09 +0000 (23:34 -0700)
committerPaul Walmsley <paul.walmsley@sifive.com>
Mon, 17 Jun 2019 09:04:05 +0000 (02:04 -0700)
commit72296bde4f4207566872ee355950a59cbc29f852
tree123d8b4f6bb514b76cfd303e17becad6217132a9
parent4fd669a8c4873b6ad54e77bc45aa37b03edc5587
riscv: dts: add initial support for the SiFive FU540-C000 SoC

Add initial support for the SiFive FU540-C000 SoC.  This is a 28nm SoC
based around the SiFive U54-MC core complex and a TileLink
interconnect.

This file is expected to grow as more device drivers are added to the
kernel.

This patch includes a fix to the QSPI memory map due to a
documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds
entries for the I2C controller, and merges all DT changes that
formerly were made dynamically by the riscv-pk BBL proxy kernel.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Loys Ollivier <lollivier@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: ShihPo Hung <shihpo.hung@sifive.com>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
arch/riscv/boot/dts/sifive/fu540-c000.dtsi [new file with mode: 0644]