i2c: qup: Correct duty cycle for FM and FM+
authorAustin Christ <austinwc@codeaurora.org>
Thu, 10 May 2018 16:13:56 +0000 (10:13 -0600)
committerWolfram Sang <wsa@the-dreams.de>
Tue, 29 May 2018 17:53:03 +0000 (19:53 +0200)
commit71fbafcc45fed7c647987495900b8f6ff29fc5aa
treeff2e9e70e5065888adeb6a99ba595c53b19b7e64
parent109b8c42b7e28ddf843488f01f243a9c9eba032b
i2c: qup: Correct duty cycle for FM and FM+

The I2C spec UM10204 Rev. 6 specifies the following timings.

           Standard      Fast Mode     Fast Mode Plus
SCL low    4.7us         1.3us         0.5us
SCL high   4.0us         0.6us         0.26us

This results in a 33%/66% duty cycle as opposed to the 50%/50% duty cycle
used for Standard-mode.

Add High Time Divider settings to correct duty cycle for FM(400kHz) and
FM+(1MHz).

Signed-off-by: Austin Christ <austinwc@codeaurora.org>
Reviewed-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
drivers/i2c/busses/i2c-qup.c