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[AArch64] Update MTE system register encodings
authorLuke Cheeseman <luke.cheeseman@arm.com>
Wed, 21 Aug 2019 09:09:56 +0000 (09:09 +0000)
committerLuke Cheeseman <luke.cheeseman@arm.com>
Wed, 21 Aug 2019 09:09:56 +0000 (09:09 +0000)
commit71d38b3c6217d6b3f0d1a50e7a59d4d78b3ecd59
tree958fc8d76988965825fac45fa5ff24b6f536db02tree | snapshot
parent6b9d7c9da591f5b9c322ca85841ffe1daa3cd7cccommit | diff
[AArch64] Update MTE system register encodings

The encodings for the system registers TFSRE0_EL1, TFSR_EL1 TFSR_EL2, TFSR_EL3
and TFSR_EL12 have been changed so that they consistently have CRn=5 and CRm=6
as per https://developer.arm.com/docs/ddi0487/latest.

Differential Revision: https://reviews.llvm.org/D65442

llvm-svn: 369505
llvm/lib/Target/AArch64/AArch64SystemOperands.td diff | blob | history
llvm/test/MC/AArch64/armv8.5a-mte.s diff | blob | history
llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt diff | blob | history
Domain: System / Toolchain;