[X86][Costmodel] Load/store i64/f64 Stride=2 VF=4 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Fri, 1 Oct 2021 13:53:32 +0000 (16:53 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Fri, 1 Oct 2021 14:48:14 +0000 (17:48 +0300)
commit71bc31b907193c294f718046ed8ef569e3d4b9fa
treefb5713656446abab008048aafc1ad8494d102e48
parent612e5b05a281b867383f52e457781d1b5ba76c2d
[X86][Costmodel] Load/store i64/f64 Stride=2 VF=4 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/j5co1qWEW - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0`
So pick cost of `4`.

For store we have:
https://godbolt.org/z/j5co1qWEW - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=4.0`
So pick cost of `4`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110837
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-store-double.ll [deleted file]
llvm/test/Analysis/CostModel/X86/interleaved-load-store-i64.ll [deleted file]
llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll