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(parent: e09418f) | patch
RISC-V: Add vssrl.vx C API tests
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Fri, 10 Feb 2023 06:24:46 +0000 (14:24 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Sun, 12 Feb 2023 10:31:41 +0000 (18:31 +0800)
commit71a1c2c67aa13ae59eef8f2b37fd364d1d18916e
treeafd3315783354d0c9d0969ad11d5e9ba6bc12980tree | snapshot
parente09418f21dd79517cc321b7999e586e0d1518942commit | diff
RISC-V: Add vssrl.vx C API tests

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vssrl_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c: New test.
18 files changed:
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c [new file with mode: 0644] blob
Domain: System / Toolchain;