fpga: zynq: Add delay after PCFG_PROG_B change
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tue, 6 Mar 2018 12:07:09 +0000 (17:37 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 9 Apr 2018 10:14:50 +0000 (12:14 +0200)
commit71723aaec5e6dbfbc401d65461fe1cae98912e79
treebd611c326ef1106c1dd17f059933d7e7d93a4350
parent31bcb3444cbd5002ca9d8f6a3a2644092748cdba
fpga: zynq: Add delay after PCFG_PROG_B change

There is delay needed after PCFG_PROGB change if
AES key source is efuse. This fixes the issue of
encrypted bitstream loading with AES efuse as key
source.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/fpga/zynqpl.c