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(parent: 50f726d) | patch
[X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.
authorCraig Topper <craig.topper@intel.com>
Tue, 9 Apr 2019 23:30:36 +0000 (23:30 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 9 Apr 2019 23:30:36 +0000 (23:30 +0000)
commit7143224272aa1e0023c6f9e4621bf6eece38249b
tree899096aca8202f2f241c7c7b273aed6dc8e53b89tree | snapshot
parent50f726d73a419b8b4c02bf2702943cbf71e5c2a4commit | diff
[X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.

Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either.
So we should ignore it in our disassembler.

The missing instructions here were found by grepping the raw tablegen class definitions in
the tablegen debug output.

llvm-svn: 358040
llvm/lib/Target/X86/X86InstrAVX512.td diff | blob | history
llvm/lib/Target/X86/X86InstrSSE.td diff | blob | history
Domain: System / Toolchain;