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(parent: 8811227) | patch
[RISCV] Add another isel optimization for (and (shl x, c2), c1)
authorCraig Topper <craig.topper@sifive.com>
Thu, 23 Sep 2021 21:09:51 +0000 (14:09 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 23 Sep 2021 21:18:07 +0000 (14:18 -0700)
commit70f50114f37e86bd4869a75b1a8313440bd55780
tree6c31dd9ac32b7bc44776a976edc1914adba94ad8tree | snapshot
parent8811227a0c0ac398857988b4fce0fb4dc699468bcommit | diff
[RISCV] Add another isel optimization for (and (shl x, c2), c1)

Turn (and (shl x, c2), c1) -> (slli (srli x, c3-c2), c3) if c1 is a
shifted mask with no leading zeros and c3 trailing zeros where c3
is greater than c2.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/shift-and.ll diff | blob | history
Domain: System / Toolchain;