intel_scu_ipc: Support 19.2M Hz crystal for CLV+ boards
authorBin Gao <bin.gao@intel.com>
Wed, 29 Feb 2012 18:45:25 +0000 (10:45 -0800)
committerbuildbot <buildbot@intel.com>
Mon, 5 Mar 2012 08:41:44 +0000 (00:41 -0800)
commit70f06dc60569414b653fb0cbd5ff1e4f58d254ce
tree874878575191e06a3bf80235f11cc5438ac68470
parentc06ba26ac38af8bffeaeca937c8779b6ef980e50
intel_scu_ipc: Support 19.2M Hz crystal for CLV+ boards

BZ: 25776

CLV A0 boards have 38.4M Hz crystal.
Moving forward all CLV+ based boards will use 19.2M Hz crystal, the
same frequency with MDFLD.
To enable old CLV A0 boards, just enable CONFIG_CTP_CRYSTAL_38M4.
For new CLV+ boards, simply disable CONFIG_CTP_CRYSTAL_38M4.
Display, audio and camera are impacted from the crystal frequency
change because they use oscillator output clocks from the Soc.

Change-Id: I755a81c700f09a505b0a554b49be3ac07c7eb4f2
Signed-off-by: Bin Gao <bin.gao@intel.com>
Reviewed-on: http://android.intel.com:8080/37049
Reviewed-by: Gross, Mark <mark.gross@intel.com>
Reviewed-by: Mai, Leonard <leonard.mai@intel.com>
Reviewed-by: Pandit, Seema <seema.pandit@intel.com>
Tested-by: Wang, Zhifeng <zhifeng.wang@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
drivers/platform/x86/Kconfig
drivers/platform/x86/intel_scu_ipc.c