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author	Yeting Kuo <yeting.kuo@sifive.com>
	Sun, 20 Nov 2022 15:11:56 +0000 (23:11 +0800)
committer	Yeting Kuo <yeting.kuo@sifive.com>
	Wed, 7 Dec 2022 04:16:36 +0000 (12:16 +0800)
commit	70de0e014013b4d97febe6704881a9a8c893d078
tree	fa12402ea8c493d6cd48bed0bce7ab454c807668	tree \| snapshot
parent	405fc404bf84fcc13e10bfac754d398199f69b7d	commit \| diff

[VP][RISCV] Add vp.fshl/fshr and RISC-V support.

The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D138379

12 files changed:

llvm/docs/LangRef.rst		diff \| blob \| history
llvm/include/llvm/IR/Intrinsics.td		diff \| blob \| history
llvm/include/llvm/IR/VPIntrinsics.def		diff \| blob \| history
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp		diff \| blob \| history
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp		diff \| blob \| history
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp		diff \| blob \| history
llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll	[new file with mode: 0644]	blob
llvm/unittests/IR/VPIntrinsicTest.cpp		diff \| blob \| history

Domain: System / Toolchain;

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