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(parent: bad7d6b) | patch
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sun, 16 Aug 2020 17:42:55 +0000 (13:42 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 24 Aug 2020 13:53:27 +0000 (09:53 -0400)
commit70cd9f5b779c04d1b32c790cb289c9f00f548b57
tree511f4178c14ded6daa87896782037f3553f3c27btree | snapshot
parentbad7d6b3735d1d855ffb07f32a272049cff085e6commit | diff
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr

Handle workitem intrinsics. There isn't really away to adequately test
this right now, since none of the known bits users are fine grained
enough to test the edge conditions. This triggers a number of
instances of the new 64-bit to 32-bit shift combine in the existing
tests.
14 files changed:
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.h diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll diff | blob | history
Domain: System / Toolchain;