[X86][Costmodel] Load/store i16 Stride=2 VF=8 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Mon, 27 Sep 2021 11:15:37 +0000 (14:15 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Mon, 27 Sep 2021 11:18:29 +0000 (14:18 +0300)
commit70c90cc5bdffe4a21e7537689ccfb958f0cb13bd
tree3b826e6b4bf3b07c00d1bd9e6c9300eda0b51c67
parent49e532aa52593921a5c4bf67fe3f170027df6f18
[X86][Costmodel] Load/store i16 Stride=2 VF=8 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/e5YE99a4P - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =2.0`
So pick cost of `6`.

For store we have:
https://godbolt.org/z/3vM4KsE1n - for intels `Block RThroughput: =3.0`; for ryzens, `Block RThroughput: <=2.0`
So pick cost of `3`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110505
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll