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(parent: 525a351) | patch
[DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits (PR30841)
authorSanjay Patel <spatel@rotateright.com>
Mon, 31 Oct 2016 23:28:45 +0000 (23:28 +0000)
committerSanjay Patel <spatel@rotateright.com>
Mon, 31 Oct 2016 23:28:45 +0000 (23:28 +0000)
commit70c5f02d25d29b1330b2747352994812d802aeaf
treebc4bf70d880e7445e25b63443de1a654311bec45tree | snapshot
parent525a3514479692be9704210f18f7ef9fa58758d9commit | diff
[DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits (PR30841)

This bug was exposed by using nsw/nuw for more aggressive folds in:
https://reviews.llvm.org/rL284844

The changes mimic the IR demanded bits logic in InstCombiner::SimplifyDemandedUseBits(),
but we can't just flip flag bits in the DAG; we have to create a new node that has the
bits cleared.

This should fix:
https://llvm.org/bugs/show_bug.cgi?id=30841

llvm-svn: 285656
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/add-sub-nsw-nuw.ll [new file with mode: 0644] blob
Domain: System / Toolchain;