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(parent: bab8c3b) | patch
RISCV: configs: tizen_visionfive2: Enable CPU_FREQ config
authorJaehoon Chung <jh80.chung@samsung.com>
Fri, 5 Jan 2024 05:25:25 +0000 (14:25 +0900)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 19 Feb 2024 00:13:48 +0000 (09:13 +0900)
commit70a7f137bc3a1583af569df9f76fce900d352807
treedd3374d4c78fee9073603fda018b6d7982b8c028tree | snapshot
parentbab8c3b3bb6f303de72b14516195e62a5da66205commit | diff
RISCV: configs: tizen_visionfive2: Enable CPU_FREQ config

Enable CPU_FREQ configuration. It was missed during version updating.

Change-Id: I6a2873886a51fb8dd3723c63c59648925a13ac9b
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
arch/riscv/configs/tizen_visionfive2_defconfig diff | blob | history
Domain: System / Kernel;