drm/i915: Store cdclk PLL reference clock under dev_priv
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 13 May 2016 20:41:33 +0000 (23:41 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 23 May 2016 18:11:15 +0000 (21:11 +0300)
commit709e05c3c46e866243f369a46ca5552a5c1e6b44
tree4bef1cb0c169fd57ff7107773e7a065aefa5512f
parent63911d7295524e59205ecfa3b2db437544c52eb8
drm/i915: Store cdclk PLL reference clock under dev_priv

Future platforms will have multiple options for the cdclk PLL reference
clock, so let's start tracking that under dev_priv alreday on SKL,
although on SKL it's always 24 MHz.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-15-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_display.c