[RISCV] Sync Zvlsseg register order as the same as vector registers.
authorHsiangkai Wang <kai.wang@sifive.com>
Wed, 22 Sep 2021 23:48:46 +0000 (07:48 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Thu, 28 Oct 2021 05:34:53 +0000 (13:34 +0800)
commit7051f73d696ebfcbb160104b9f925c8a98e557c7
treeb9112af1a4c5754d338815fce71de0c86bbb326a
parent130055647922ffa9dd9abd5a838727773f73c48a
[RISCV] Sync Zvlsseg register order as the same as vector registers.

Sync the order of Zvlsseg registers with vector registers to avoid
unnecessary register copies between vector instructions and zvlsseg
instructions.

Differential Revision: https://reviews.llvm.org/D110250
14 files changed:
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll