[RISCV] Lower interleave2 intrinsics to vsseg2
authorLuke Lau <luke@igalia.com>
Tue, 27 Jun 2023 12:41:46 +0000 (13:41 +0100)
committerLuke Lau <luke@igalia.com>
Wed, 5 Jul 2023 18:24:05 +0000 (19:24 +0100)
commit70093fcf6c324da6f98a1e606afdaa9d04b5d1fd
tree2bc3c7e06a942aae442a90f7b00f7eca9ce30cba
parentd914686da25d4744fe5ebf565a8b4c0cd23016ce
[RISCV] Lower interleave2 intrinsics to vsseg2

This patch teaches the RISCV TargetLowering class to lower interleave
intrinsics to vsseg2, so it can lower interleaved stores for scalable vectors.
Previously, we could only lower stores of interleaves for fixed length vectors
with vector shuffles.

This uses the lowerInterleaveIntrinsic interface for the interleaved
access pass that was added in D146218, and subsumes the DAG combine
approach taken in D144175

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D153864
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll