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(parent: 59908fc) | patch
[RISCV] Change ConstraintMask in RISCVII enum to be shifted left. NFC
authorCraig Topper <craig.topper@sifive.com>
Sun, 10 Jan 2021 03:56:57 +0000 (19:56 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sun, 10 Jan 2021 04:22:07 +0000 (20:22 -0800)
commit6fc7a92eeeb5c47754b875bf6cf1b84687ebe693
tree9d4581105f6a05c302bb1abd60edf1a5ee7fbedatree | snapshot
parent59908fc06ace351dad0b82b38c793f7b92ab4530commit | diff
[RISCV] Change ConstraintMask in RISCVII enum to be shifted left. NFC

This makes the mask align with the position of the bits in TSFlags
which is a little more logical.

I might be adding more fields to TSFlags and some might be single
bits where just ANDing with mask to test the bit would make sense.

While there rename TargetFlags in validateInstruction to reflect
that it's just the constraint bits.
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp diff | blob | history
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h diff | blob | history
Domain: System / Toolchain;