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(parent: e1b2536) | patch
Do not emit intermediate register for zero FP immediate
authorRenato Golin <renato.golin@linaro.org>
Thu, 23 Oct 2014 15:31:50 +0000 (15:31 +0000)
committerRenato Golin <renato.golin@linaro.org>
Thu, 23 Oct 2014 15:31:50 +0000 (15:31 +0000)
commit6fb9c2ea702116381c430a221eaf00d1a2bb17b2
treeb2f500624fb9ae0a8a4512a4ca62064e79bfba8dtree | snapshot
parente1b25368f0cec7380d36f26a64c44df7bc7db298commit | diff
Do not emit intermediate register for zero FP immediate

This updates check for double precision zero floating point constant to allow
use of instruction with immediate value rather than temporary register.
Currently "a == 0.0", where "a" is of "double" type generates:

vmov.i32        d16, #0x0
vcmpe.f64       d0, d16

With this change it becomes:

vcmpe.f64        d0, #0

Patch by Sergey Dmitrouk.

llvm-svn: 220486
llvm/lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
llvm/test/CodeGen/ARM/fpcmp-f64-neon-opt.ll [new file with mode: 0644] blob
Domain: System / Toolchain;