[X86] Redefine MOVSS/MOVSD instructions to take VR128 regclass as input instead of...
authorCraig Topper <craig.topper@intel.com>
Wed, 4 Oct 2017 17:20:12 +0000 (17:20 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 4 Oct 2017 17:20:12 +0000 (17:20 +0000)
commit6fb55716e9c77e716f4ac25abc84687eac29f848
tree07097be59b5b39b860012ae8d20d8248fb9a6506
parent5a09996ff70ee0cd533c8d401f3924aee662551f
[X86] Redefine MOVSS/MOVSD instructions to take VR128 regclass as input instead of FR32/FR64

This patch redefines the MOVSS/MOVSD instructions to take VR128 as its second input. This allows the MOVSS/SD->BLEND commute to work without requiring a COPY to be inserted.

This should fix PR33079

Overall this looks to be an improvement in the generated code. I haven't checked the EXPENSIVE_CHECKS build but I'll do that and update with results.

Differential Revision: https://reviews.llvm.org/D38449

llvm-svn: 314914
16 files changed:
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrSSE.td
llvm/test/CodeGen/X86/buildvec-insertvec.ll
llvm/test/CodeGen/X86/lower-vec-shift.ll
llvm/test/CodeGen/X86/psubus.ll
llvm/test/CodeGen/X86/vector-blend.ll
llvm/test/CodeGen/X86/vector-compare-results.ll
llvm/test/CodeGen/X86/vector-rotate-128.ll
llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
llvm/test/CodeGen/X86/vector-shift-shl-128.ll
llvm/test/CodeGen/X86/vector-trunc-math.ll
llvm/test/CodeGen/X86/vector-trunc.ll
llvm/test/CodeGen/X86/vshift-4.ll
llvm/test/CodeGen/X86/x86-shifts.ll