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author	Wang, Pengfei <pengfei.wang@intel.com>
	Tue, 10 Aug 2021 03:18:40 +0000 (11:18 +0800)
committer	Wang, Pengfei <pengfei.wang@intel.com>
	Tue, 10 Aug 2021 04:46:01 +0000 (12:46 +0800)
commit	6f7f5b54c81be59ec7876649d1f9aa6b104658ec
tree	b695ae7f4e450d1a6e818e40b5c51871e0c82753	tree \| snapshot
parent	b978df4af4c8a668550fa035b70795312bf41f44	commit \| diff

[X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105263

73 files changed:

clang/docs/ClangCommandLineReference.rst		diff \| blob \| history
clang/docs/LanguageExtensions.rst		diff \| blob \| history
clang/docs/ReleaseNotes.rst		diff \| blob \| history
clang/include/clang/Basic/BuiltinsX86.def		diff \| blob \| history
clang/include/clang/Driver/Options.td		diff \| blob \| history
clang/lib/Basic/Targets/X86.cpp		diff \| blob \| history
clang/lib/Basic/Targets/X86.h		diff \| blob \| history
clang/lib/CodeGen/CGBuiltin.cpp		diff \| blob \| history
clang/lib/CodeGen/TargetInfo.cpp		diff \| blob \| history
clang/lib/Headers/CMakeLists.txt		diff \| blob \| history
clang/lib/Headers/avx512fp16intrin.h	[new file with mode: 0644]	blob
clang/lib/Headers/avx512vlfp16intrin.h	[new file with mode: 0644]	blob
clang/lib/Headers/cpuid.h		diff \| blob \| history
clang/lib/Headers/immintrin.h		diff \| blob \| history
clang/test/CodeGen/X86/avx512fp16-abi.c	[new file with mode: 0644]	blob
clang/test/CodeGen/X86/avx512fp16-builtins.c	[new file with mode: 0644]	blob
clang/test/CodeGen/X86/avx512vlfp16-builtins.c	[new file with mode: 0644]	blob
clang/test/CodeGen/attr-target-x86.c		diff \| blob \| history
clang/test/Driver/x86-target-features.c		diff \| blob \| history
clang/test/Preprocessor/predefined-arch-macros.c		diff \| blob \| history
clang/test/Preprocessor/x86_target_features.c		diff \| blob \| history
llvm/docs/ReleaseNotes.rst		diff \| blob \| history
llvm/include/llvm/IR/Intrinsics.td		diff \| blob \| history
llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h		diff \| blob \| history
llvm/include/llvm/Support/X86TargetParser.def		diff \| blob \| history
llvm/include/llvm/Target/TargetSelectionDAG.td		diff \| blob \| history
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp		diff \| blob \| history
llvm/lib/Support/Host.cpp		diff \| blob \| history
llvm/lib/Support/X86TargetParser.cpp		diff \| blob \| history
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp		diff \| blob \| history
llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp		diff \| blob \| history
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h		diff \| blob \| history
llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h		diff \| blob \| history
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86.td		diff \| blob \| history
llvm/lib/Target/X86/X86CallingConv.td		diff \| blob \| history
llvm/lib/Target/X86/X86FastISel.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelLowering.h		diff \| blob \| history
llvm/lib/Target/X86/X86InstrAVX512.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrCompiler.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrFormats.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86InstrInfo.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrVecCompiler.td		diff \| blob \| history
llvm/lib/Target/X86/X86RegisterInfo.td		diff \| blob \| history
llvm/lib/Target/X86/X86Schedule.td		diff \| blob \| history
llvm/lib/Target/X86/X86Subtarget.h		diff \| blob \| history
llvm/lib/Target/X86/X86TargetTransformInfo.cpp		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll	[new file with mode: 0644]	blob
llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16.ll	[new file with mode: 0644]	blob
llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16.ll	[new file with mode: 0644]	blob
llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16.ll	[new file with mode: 0644]	blob
llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir		diff \| blob \| history
llvm/test/CodeGen/X86/avx512fp16-insert-extract.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/avx512fp16-mov.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/avx512fp16-mscatter.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/avx512fp16-subv-broadcast-fp16.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/avx512fp16vl-intrinsics.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/fp128-cast-strict.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pseudo_cmov_lower-fp16.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir		diff \| blob \| history
llvm/test/MC/Disassembler/X86/avx512fp16.txt	[new file with mode: 0644]	blob
llvm/test/MC/X86/avx512fp16.s	[new file with mode: 0644]	blob
llvm/test/MC/X86/intel-syntax-avx512fp16.s	[new file with mode: 0644]	blob
llvm/test/MachineVerifier/test_copy_physregs_x86.mir		diff \| blob \| history
llvm/utils/TableGen/X86DisassemblerTables.cpp		diff \| blob \| history
llvm/utils/TableGen/X86DisassemblerTables.h		diff \| blob \| history
llvm/utils/TableGen/X86RecognizableInstr.cpp		diff \| blob \| history
llvm/utils/TableGen/X86RecognizableInstr.h		diff \| blob \| history

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