Add alignment value to allowsUnalignedMemoryAccess
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sun, 27 Jul 2014 17:46:40 +0000 (17:46 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Sun, 27 Jul 2014 17:46:40 +0000 (17:46 +0000)
commit6f2a526101bfef214aef8cae8dba4a9cce55b6fa
tree7fdf854c43b57af4354e0d48aec858b4e72b18be
parentb3cd5a1037d71e33b2519fcaf66e2978679f3c22
Add alignment value to allowsUnalignedMemoryAccess

Rename to allowsMisalignedMemoryAccess.

On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment,
and don't need to be split into multiple accesses. Vector loads with
an alignment of the element type are not uncommon in OpenCL code.

llvm-svn: 214055
23 files changed:
llvm/include/llvm/Target/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/Mips/Mips16ISelLowering.cpp
llvm/lib/Target/Mips/Mips16ISelLowering.h
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/lib/Target/Mips/MipsSEISelLowering.h
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/R600/SIISelLowering.cpp
llvm/lib/Target/R600/SIISelLowering.h
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.h
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/XCore/XCoreISelLowering.cpp
llvm/test/CodeGen/R600/unaligned-load-store.ll