i965: fix cycle estimates when there's a pipeline stall
authorConnor Abbott <cwabbott0@gmail.com>
Fri, 5 Jun 2015 23:20:57 +0000 (19:20 -0400)
committerConnor Abbott <cwabbott0@gmail.com>
Fri, 30 Oct 2015 06:18:53 +0000 (02:18 -0400)
commit6f231fddff1661c2ca2cfb7bb7a0e6a970bcbf40
treefa2ab86c12d4760947fdd7a671651e182ffe0c90
parent04c42f3ab56a19089b46dea48615aeef8b8225da
i965: fix cycle estimates when there's a pipeline stall

The issue time for an instruction is how many cycles it takes to
actually put it into the pipeline. If there's a pipeline stall that
causes the instruction to be delayed, we should first take that into
account to figure out when the instruction would start executing and
*then* add the issue time. The old code had it backwards, and so we
would underestimate the total time whenever we thought there would be a
pipeline stall by up to the issue time of the instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp