dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible
authorConor Dooley <conor.dooley@microchip.com>
Tue, 23 Aug 2022 18:33:18 +0000 (19:33 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 13 Oct 2022 00:05:16 +0000 (17:05 -0700)
commit6e965c9bd7388762b302dca5852eb25cbe9cc085
treec0967bdf60b93cd46762858e18ae1377bb630fd3
parent826249942679a110353e71a1d92764fcf43e7cf7
dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible

While "real" hardware might not use the compatible string "riscv,plic0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.

riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed:
        'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic']
        'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic']
        'sifive,plic-1.0.0' was expected
        'thead,c900-plic' was expected
riscv-virt.dtb: plic@c000000: '#address-cells' is a required property

Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220823183319.3314940-3-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml