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riscv:dts:drm
authorshengyang.chen <shengyang.chen@starfivetech.com>
Thu, 15 Sep 2022 10:52:27 +0000 (18:52 +0800)
committershengyang.chen <shengyang.chen@starfivetech.com>
Thu, 15 Sep 2022 10:52:27 +0000 (18:52 +0800)
commit6e4394acfd35be2b64bdeb2f1bc6c92eb7fb97b7
treedf78b0f8850ec73d402d2720f2e475b8f51788e5tree | snapshot
parentd0eb9d07b37231f2537cf87cbe3735a2786e95f1commit | diff
riscv:dts:drm

update changing of dts compatible value

Signed-off-by: shengyang.chen<shengyang.chen@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi diff | blob | history
Domain: System / Kernel;