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(parent: ccf22ef) | patch
[AMDGPU] Change register type for v32 vectors
authorStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Tue, 16 Jul 2019 20:06:00 +0000 (20:06 +0000)
committerStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Tue, 16 Jul 2019 20:06:00 +0000 (20:06 +0000)
commit6e0fa292c22cde726b4ddb53cf1fa8c649384030
tree0eab7cef5f01384cbbb4618c6be05e2edac66921tree | snapshot
parentccf22ef94c4a94f7598f51a70445fdec8f8a1bc8commit | diff
[AMDGPU] Change register type for v32 vectors

When it is AReg_1024 this results in unnecessary copying into
AGPRs of a 32 element vectors even though they are not intended
for an mfma instruction.

Differential Revision: https://reviews.llvm.org/D64815

llvm-svn: 366252
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/v1024.ll [new file with mode: 0644] blob
Domain: System / Toolchain;