MIPS: KVM: Fix CACHE triggered exception emulation
authorJames Hogan <james.hogan@imgtec.com>
Thu, 9 Jun 2016 09:50:46 +0000 (10:50 +0100)
committerPaolo Bonzini <pbonzini@redhat.com>
Tue, 14 Jun 2016 08:59:45 +0000 (10:59 +0200)
commit6df82a7b88dc9b0b519765562b005ef9196d812a
treef9dc243efafe9ba7772882ea166e11bb7d7e5743
parentcc81e9486202345d6ca56495cf8b5f3d03fbc563
MIPS: KVM: Fix CACHE triggered exception emulation

When emulating TLB miss / invalid exceptions during CACHE instruction
emulation, be sure to set up the correct PC and host_cp0_badvaddr state
for the kvm_mips_emlulate_tlb*_ld() function to pick up for guest EPC
and BadVAddr.

PC needs to be rewound otherwise the guest EPC will end up pointing at
the next instruction after the faulting CACHE instruction.

host_cp0_badvaddr must be set because guest CACHE instructions trap with
a Coprocessor Unusable exception, which doesn't update the host BadVAddr
as a TLB exception would.

This doesn't tend to get hit when dynamic translation of emulated
instructions is enabled, since only the first execution of each CACHE
instruction actually goes through this code path, with subsequent
executions hitting the SYNCI instruction that it gets replaced with.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/mips/kvm/emulate.c