dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 3 Oct 2023 10:47:59 +0000 (12:47 +0200)
committerRob Herring <robh@kernel.org>
Wed, 4 Oct 2023 13:33:11 +0000 (08:33 -0500)
commit6df241aacef5f9175b818a80c2ee018697efabc0
treead68f816b1a01c496f9a9efad148873046b6d28b
parent5d007ffdf6025fe83e497c44ed7c8aa8f150c4d1
dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example

The unit address in the example does not match the reg property.
Correct the unit address to match reality.

Fixes: 3e7bf4685e42786d ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/7b93655219a6ad696dd3faa9f36fde6b094694a9.1696330005.git.geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml