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(parent: b18d6f0) | patch
RISC-V: Disable preemption before enabling interrupts
authorAtish Patra <atish.patra@wdc.com>
Tue, 2 Oct 2018 19:14:58 +0000 (12:14 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 23 Oct 2018 00:03:36 +0000 (17:03 -0700)
commit6db170ff4c088caaf7806c00b29a55f6df07d7b6
treed91d87868100acbbf8436728ebcdccc152689766tree | snapshot
parentb18d6f05252d6b3f725c08d8831a46b003df5b6bcommit | diff
RISC-V: Disable preemption before enabling interrupts

Currently, irq is enabled before preemption disabling happens.
If the scheduler fired right here and cpu is scheduled then it
may blow up.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
[Atish: Commit text and code comment formatting update]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/smpboot.c diff | blob | history
Domain: System / Kernel;