clk: axs10x: introduce AXS10X pll driver
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Wed, 21 Jun 2017 19:16:26 +0000 (22:16 +0300)
committerStephen Boyd <sboyd@codeaurora.org>
Mon, 17 Jul 2017 18:50:59 +0000 (11:50 -0700)
commit6d7489c74a6ed73b4751b58b56c247bedd780a78
tree158dbdd8dd805a4c4726b5cf72874197f202d5db
parent5771a8c08880cdca3bfb4a3fc6d309d6bba20877
clk: axs10x: introduce AXS10X pll driver

AXS10X boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.

Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the
following devices:
 * ARC core on AXC CPU tiles.
 * ARC PGU on ARC SDP Mainboard.
and more to come later.

By this patch we add support for two plls (arc core pll and pgu pll),
so we had to use two different init types: CLK_OF_DECLARE for arc core pll and
regular probing for pgu pll.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
[sboyd@codeaurora.org: Silence dubious !x & y sparse warning,
make of_axs10x_pll_clk_setup() unregister clk on failure]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Documentation/devicetree/bindings/clock/snps,pll-clock.txt [new file with mode: 0644]
MAINTAINERS
drivers/clk/axs10x/Makefile
drivers/clk/axs10x/pll_clock.c [new file with mode: 0644]