projects / platform / upstream / glibc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 659ca26) | patch
aarch64: Guess L1 cache linesize for aarch64
authorRichard Henderson <rth@twiddle.net>
Fri, 3 Nov 2017 16:38:16 +0000 (16:38 +0000)
committerSzabolcs Nagy <szabolcs.nagy@arm.com>
Fri, 3 Nov 2017 16:40:27 +0000 (16:40 +0000)
commit6d58ce5e5072945d44f2dba83ad16cd6febd056c
tree35cd666ef3c3feb4130d963d08620734ef4bc51ctree | snapshot
parent659ca267360e1c1f64eea9205bb81cb5e9049908commit | diff
aarch64: Guess L1 cache linesize for aarch64

Using the cache hierarchy linesize minimum in CTR_EL0.
See the comment within the code for rationale.

* sysdeps/unix/sysv/linux/aarch64/sysconf.c: New file.
ChangeLog diff | blob | history
sysdeps/unix/sysv/linux/aarch64/sysconf.c [new file with mode: 0644] blob
Domain: System / Toolchain;