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(parent: 2bd470f) | patch
drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume
authorMugunthan V N <mugunthanvnm@ti.com>
Tue, 18 Jun 2013 09:34:35 +0000 (15:04 +0530)
committerDavid S. Miller <davem@davemloft.net>
Thu, 20 Jun 2013 01:33:58 +0000 (18:33 -0700)
commit6d3d76f877ca061911343d5d1650458906fdf0ea
tree769a950b177667066eee283deda5b40bfcf8218ftree | snapshot
parent2bd470fc08cbbfd4f2e53a620362806620d217edcommit | diff
drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume

Due to some hardware integration issue, CPSW sliver modules requires a
reset across suspend/resume cycle for a successful clock gating to
CPGMAC (CPSW and Davinci MDIO) in AM335x PG1.0.
This issue is fixed in PG2.x, though to support suspend/resume on PG1.0
this reset is required.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/ti/cpsw.c diff | blob | history
Domain: System / Kernel;