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(parent: bd98df5) | patch
intel/fs/ra/xe2: Scale up register allocation granularity by 2x on Xe2+ platforms.
authorFrancisco Jerez <currojerez@riseup.net>
Wed, 29 Jun 2022 00:49:38 +0000 (17:49 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Thu, 21 Sep 2023 00:19:36 +0000 (17:19 -0700)
commit6d39b3d6ae900dec488131b33b61644b25956a3b
treec24c6a5cb1df4f78e31585587718718c9a2cf2d4tree | snapshot
parentbd98df5d8ece369b5a82100cd0206338c889c3b5commit | diff
intel/fs/ra/xe2: Scale up register allocation granularity by 2x on Xe2+ platforms.

v2: Fix spill register allocation.  Switch to brw_reg::nr
    representation in fake 256b units.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
src/intel/compiler/brw_eu.h diff | blob | history
src/intel/compiler/brw_fs_reg_allocate.cpp diff | blob | history
Domain: Graphics System / GL;