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(parent: 93917ad) | patch
rseq/selftests: Add support for RISC-V
authorVincent Chen <vincent.chen@sifive.com>
Tue, 8 Mar 2022 08:32:53 +0000 (16:32 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 22 Mar 2022 21:45:19 +0000 (14:45 -0700)
commit6d1a6f464efd596779d1b272b3dc8170c5fa189f
tree35f6444e6bae8e031bcefcb457bd0de3ebbfe16atree | snapshot
parent93917ad50972e6298885d81b37b6a8602eb0b188commit | diff
rseq/selftests: Add support for RISC-V

Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
tools/testing/selftests/rseq/param_test.c diff | blob | history
tools/testing/selftests/rseq/rseq-riscv.h [new file with mode: 0644] blob
tools/testing/selftests/rseq/rseq.h diff | blob | history
Domain: System / Kernel;