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ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
authorVignesh R <vigneshr@ti.com>
Tue, 25 Sep 2018 05:21:51 +0000 (10:51 +0530)
committerTony Lindgren <tony@atomide.com>
Fri, 28 Sep 2018 17:26:01 +0000 (10:26 -0700)
commit6d0af44a82be87c13f2320821e9fbb8b8cf5a56f
treee952eef998e6c674aba5f8cff9c31ffb6db5782ftree | snapshot
parent20bcd4a4d76d7474047ff4539e7d65b990bb2556commit | diff
ARM: dts: dra7: Fix up unaligned access setting for PCIe EP

Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.

Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/dra7.dtsi diff | blob | history
Domain: System / Kernel;