projects / platform / upstream / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5898cba) | patch
i965: Use proper TCS barrier ID bits for Ivybridge/Baytrail.
authorKenneth Graunke <kenneth@whitecape.org>
Thu, 24 Dec 2015 23:26:55 +0000 (15:26 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 28 Dec 2015 21:16:57 +0000 (13:16 -0800)
commit6ceabb72eae938570d9aa0ae054bab1df421d79a
tree81b08010e218d328f54621097282ade2a0359debtree | snapshot
parent5898cbae2479874a6206e27e6b73a3ba244a2094commit | diff
i965: Use proper TCS barrier ID bits for Ivybridge/Baytrail.

Gen7 uses bits 15:12 while Gen7+ uses bits 16:13.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp diff | blob | history
Domain: Graphics System / GL;