net: stmmac: use interrupt mode INTM=1 for multi-MSI
authorWong, Vee Khee <vee.khee.wong@intel.com>
Thu, 25 Mar 2021 17:39:16 +0000 (01:39 +0800)
committerDavid S. Miller <davem@davemloft.net>
Fri, 26 Mar 2021 00:37:30 +0000 (17:37 -0700)
commit6ccf12ae111e49324b439410066e8cc359aeee6d
tree1c268024e10fcf3e50158107d46348d624c3ed23
parentb42446b9b37ba444ba12d89dd9d45c2b68768f24
net: stmmac: use interrupt mode INTM=1 for multi-MSI

For interrupt mode INTM=0, TX/RX transfer complete will trigger signal
not only on sbd_perch_[tx|rx]_intr_o (Transmit/Receive Per Channel) but
also on the sbd_intr_o (Common).

As for multi-MSI implementation, setting interrupt mode INTM=1 is more
efficient as each TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.

Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.

Signed-off-by: Wong, Vee Khee <vee.khee.wong@intel.com>
Co-developed-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
include/linux/stmmac.h