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(parent: 1561380) | patch
clk: renesas: rzg2l: Add PLL5_4 clk mux support
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 30 Apr 2022 11:41:49 +0000 (12:41 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:21 +0000 (12:10 +0200)
commit6cc859cae9aa8c42e8347e2806232bdffeb1b33d
treecddfa732f740cf19681215f34424b31f32c5f058tree | snapshot
parent1561380ee72f55e3a86856ee046532c18d3e9855commit | diff
clk: renesas: rzg2l: Add PLL5_4 clk mux support

Add PLL5_4 clk mux support to select clock from clock
sources FOUTPOSTDIV and FOUT1PH0.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rzg2l-cpg.c diff | blob | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | history
Domain: System / Kernel;