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(parent: f76d3b8) | patch
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
authorCraig Topper <craig.topper@sifive.com>
Wed, 2 Mar 2022 18:55:18 +0000 (10:55 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 2 Mar 2022 19:22:46 +0000 (11:22 -0800)
commit6cb42cd6669785f3b611106e1b6b38bbe65733a9
treee0095ebd6816f18c2550713d1a7c137a19c84868tree | snapshot
parentf76d3b800f7341882ea93db47cc8f28d94e74f1ccommit | diff
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.

Until Zfinx is supported in CodeGen we need to convert all Zfinx
register classes to GPR.

Remove the zfinx-types.ll test which didn't test anything meaningful
since -mattr=zfinx isn't implemented completely in llc.

Follow up to D93298.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll diff | blob | history
llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll diff | blob | history
llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll diff | blob | history
llvm/test/CodeGen/RISCV/zfinx-types.ll [deleted file] blob | history
Domain: System / Toolchain;