[X86] Use PreprocessISelDAG to convert vector sra/srl/shl to the X86 specific variabl...
authorCraig Topper <craig.topper@intel.com>
Thu, 28 Feb 2019 07:21:26 +0000 (07:21 +0000)
committerCraig Topper <craig.topper@intel.com>
Thu, 28 Feb 2019 07:21:26 +0000 (07:21 +0000)
commit6ca7398a1e9481c950d60f2200b297fd9c2d67a7
tree8711e2d3ca544c123f317110ceb3554807fd47be
parente931931b34cebf132b601374399f021105434c32
[X86] Use PreprocessISelDAG to convert vector sra/srl/shl to the X86 specific variable shift ISD opcodes.

These allows use to use the same set of isel patterns for sra/srl/shl which are undefined for out of range shifts and intrinsic shifts which aren't undefined.

Doing this late allows DAG combine to have every opportunity to optimize the sra/srl/shl nodes.

This removes about 7000 bytes from the isel table and simplies the td files.

llvm-svn: 355071
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrSSE.td