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AArch64: Set shift bit of TLSLE HI12 add instruction
authorLei Liu <lei.liu2@windriver.com>
Wed, 21 Sep 2016 07:41:41 +0000 (07:41 +0000)
committerLei Liu <lei.liu2@windriver.com>
Wed, 21 Sep 2016 07:41:41 +0000 (07:41 +0000)
commit6c87f2352626d999530fde97a4ad226311bf3839
tree942ae3388bd0ac76603a7cb6d7a43a5bea398128tree | snapshot
parent6f99d2433b0a2a0af6b54dddbb3b752d9d4c8a18commit | diff
AArch64: Set shift bit of TLSLE HI12 add instruction

Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model.  This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.

Reviewers: t.p.northover, peter.smith, rovka

Subscribers: salim.nasser, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D24702

llvm-svn: 282057
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp diff | blob | history
llvm/test/MC/AArch64/tls-add-shift.s [new file with mode: 0644] blob
Domain: System / Toolchain;