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author	Craig Topper <craig.topper@sifive.com>
	Thu, 9 Sep 2021 22:17:51 +0000 (15:17 -0700)
committer	Craig Topper <craig.topper@sifive.com>
	Fri, 10 Sep 2021 16:03:20 +0000 (09:03 -0700)
commit	6c7cadb8c155befbb0fdd058dfb5dbaa0b9aa40a
tree	66a5399db51cd54484d8f4be9a36114134aa65bc	tree \| snapshot
parent	4e7ac6facad6d6c895c750a232d3786defedcc7b	commit \| diff

[RISCV] Teach vsetvli insertion that stores don't use the policy bits in vtype.

This can avoid a vsetvl after a tail undisturbed operation.

Differential Revision: https://reviews.llvm.org/D109549

15 files changed:

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll		diff \| blob \| history

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