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(parent: 5c36557) | patch
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
authorCraig Topper <craig.topper@intel.com>
Thu, 5 Apr 2018 04:42:01 +0000 (04:42 +0000)
committerCraig Topper <craig.topper@intel.com>
Thu, 5 Apr 2018 04:42:01 +0000 (04:42 +0000)
commit6c4e08c835105ba48630f208a9c49ca2b54e7403
treedaca3c059213f8d74af127a173f2e7434687e3b0tree | snapshot
parent5c36557426db25e13714099fb04defc7c8205ac1commit | diff
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.

We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion.

llvm-svn: 329252
llvm/test/CodeGen/X86/sse2-schedule.ll diff | blob | history
Domain: System / Toolchain;