ARM: keystone: ddr3: workaround for ddr3a/3b memory issue
authorMurali Karicheri <m-karicheri2@ti.com>
Wed, 10 Sep 2014 12:54:59 +0000 (15:54 +0300)
committerTom Rini <trini@ti.com>
Thu, 18 Sep 2014 01:06:56 +0000 (21:06 -0400)
commit6c343825dd8852843ee7426c579cb55520ad2fc8
treeeadbd6bb5af57cc360c6a23bd9708e1bb86573f8
parentc292adae170fa8c27dca75963bdb0a9afc640e57
ARM: keystone: ddr3: workaround for ddr3a/3b memory issue

This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
arch/arm/cpu/armv7/keystone/ddr3.c
arch/arm/include/asm/arch-keystone/ddr3.h
arch/arm/include/asm/arch-keystone/hardware.h
board/ti/ks2_evm/ddr3_k2hk.c