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[Power9] Processor Model for Scheduling
authorEhsan Amiri <amehsan@ca.ibm.com>
Mon, 19 Dec 2016 13:35:45 +0000 (13:35 +0000)
committerEhsan Amiri <amehsan@ca.ibm.com>
Mon, 19 Dec 2016 13:35:45 +0000 (13:35 +0000)
commit6c17bb0eb7a1d70a1e2c740a3508c4b295c7deef
tree413a4fdfd35fe4bbf4d508b9e79296cc723921cdtree | snapshot
parentc0eb9963180ef33debbd4f0a0e752eb8187a80c5commit | diff
[Power9] Processor Model for Scheduling

PWR9 processor model for instruction scheduling. A subsequent patch will migrate
PWR9 to Post RA MIScheduler.
https://reviews.llvm.org/D24525

llvm-svn: 290102
llvm/lib/Target/PowerPC/P9InstrResources.td [new file with mode: 0644] blob
llvm/lib/Target/PowerPC/PPC.td diff | blob | history
llvm/lib/Target/PowerPC/PPCSchedule.td diff | blob | history
llvm/lib/Target/PowerPC/PPCScheduleP9.td [new file with mode: 0644] blob
Domain: System / Toolchain;