[AMDGPU] Mark s_barrier as having side effects but not accessing memory.
authorJay Foad <jay.foad@gmail.com>
Fri, 6 Sep 2019 10:07:28 +0000 (10:07 +0000)
committerJay Foad <jay.foad@gmail.com>
Fri, 6 Sep 2019 10:07:28 +0000 (10:07 +0000)
commit6c0204c794ba143ce6817f695e03fd9f49cd4ed8
tree1ce58102bd39e3c4b6e0962fa1f4321975755608
parent68df9dc09818289ac5b40d0916bb479a358a8e18
[AMDGPU] Mark s_barrier as having side effects but not accessing memory.

Summary:
This fixes poor scheduling in a function containing a barrier and a few
load instructions.

Without this fix, ScheduleDAGInstrs::buildSchedGraph adds an artificial
edge in the dependency graph from the barrier instruction to the exit
node representing live-out latency, with a latency of about 500 cycles.
Because of this it thinks the critical path through the graph also has
a latency of about 500 cycles. And because of that it does not think
that any of the load instructions are on the critical path, so it
schedules them with no regard for their (80 cycle) latency, which gives
poor results.

Reviewers: arsenm, dstuttard, tpr, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67218

llvm-svn: 371192
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
llvm/test/CodeGen/AMDGPU/schedule-barrier.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll