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(parent: 5c7fe5d) | patch
[MI scheduler] Fix VADD and VSUB in cortex-a57 model
authorEugene Leviant <eleviant@accesssoftek.com>
Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)
committerEugene Leviant <eleviant@accesssoftek.com>
Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)
commit6bc35a93e6be166ec25cc42ab081ea161740ba3b
treedd47eed5f215d3bf5f551553d3e940621c9dd306tree | snapshot
parent5c7fe5df5312d02c027531a9121e7ac9e8e01b73commit | diff
[MI scheduler] Fix VADD and VSUB in cortex-a57 model

This patch fixes instregex for interger vector add/sub instructions

Differential revision: https://reviews.llvm.org/D40254

llvm-svn: 318749
llvm/lib/Target/ARM/ARMScheduleA57.td diff | blob | history
llvm/test/CodeGen/ARM/cortex-a57-misched-vadd.ll [new file with mode: 0644] blob
llvm/test/CodeGen/ARM/cortex-a57-misched-vsub.ll [new file with mode: 0644] blob
Domain: System / Toolchain;