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(parent: ec73fba) | patch
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Tue, 14 Mar 2023 12:43:57 +0000 (20:43 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 28 Mar 2023 03:23:05 +0000 (12:23 +0900)
commit6bad8929356b5ae31dd82239712bf8d7d9e360b1
tree68ca659f244d0af8263a40234d9b762869c4447atree | snapshot
parentec73fba8dd3a16218fbb4974cc92fa8676ceb404commit | diff
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
include/dt-bindings/reset/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;